Contacts facilitate the electrical connection of semiconductor device components. Various methods and means may be employed in the forming of such contacts including photolithography. Photolitographic processes are often employed to pattern various layers on a wafer in order to produce circuit features positioned as specified in a circuit diagram. Such processes generally entail operations such as depositing a layer of photoresist onto a layer to be patterned, and exposing the photoresist using an exposure tool and a template. These templates are known as reticles or masks. During the exposure process, the reticle is imaged onto the photoresist by directing radiant energy (e.g., ultraviolet light) through the reticle. The image projected onto the photoresist selectively exposes it in a desired pattern.
Exposure tools may be limited in their capacity to facilitate the proper dimensioning and alignment of contact structures in the semiconductor device fabrication process. One limitation of such exposure tools is their resolution limit. The resolution limit of an exposure tool is defined as the minimum feature dimension that the exposure tool can repeatedly expose onto the resist, and is a function of amongst other things its depth of focus. In addition, limitations in the alignment capability of the exposure tool may be exposed by the necessity of precisely aligning the respective structures that constitute the semiconductor device. The misalignment of such device structures may result in a fatal defect of the semiconductor device.
Utilizing the aforementioned exposure tools, there are two methods of making contact to the gate material filling the trenches in a trench power MOSFET. The first method illustrated schematically in FIG. 1 requires the use of a mask (not shown) to pattern a polysilicon layer 101 after it is deposited onto substrate 103 and fills trench grooves 104 formed in substrate 103. In the area of the main device, called the active area, the polysilicon is etched back with a recess formed in the polysilicon material filling the trench grooves as relative to the front surface of the silicon substrate. In the area of the gate bus, the polycrystalline layer of the deposited silicon is patterned so that a portion of the layer is in electrical contact with the material filling the trench located there. An extension of this layer 101a is formed on the surface of a thick oxide layer 105, called field oxide, where contact can be made to gate bus metal 107. In the termination area the polysilicon film can be etched away or left to form field plates in the edge termination region. If the polysilicon film is etched away, a metal stripe 109 along the edge of the die may provide the function of the field plate electrode, as is shown in FIGS. 1 and 2. Also shown in FIG. 1 is source contact 111, source regions 113, contact implants 115, and body well 117.
The second method is illustrated by FIG. 2. This method does not employ a polysilicon mask, as the polysilicon layer is etched back from the entire front surface of the substrate during the device fabrication process. In addition, the trench is formed wider locally within the gate bus area, which facilitates easy contact to be made to the polysilicon material filling the wide trench 201.
A drawback of the first method is the large height differences found in the topology of the front surface. Because of the restricted depth of focus of exposure tools, the uneven topography of the real estate surrounding the gate bus area presents a severe limitation to the minimum feature size which can be printed by photolithography. This is because the differences in the height dimensions that are presented by such topologies test the resolution limit of exposure tools. The second method solves the issue of the height difference in the surface topology but has to rely on the alignment capability of the exposure tool, where even a small misalignment may result in an increased danger of leakage current or even an electric short between the gate and source electrodes. Moreover, the second method does not facilitate an easy integration of polysilicon devices with the main MOSFET, as the entire polysilicon layer from which such may be formed is etched away.